This application claims the benefit of Korean patent application No. P2001-18635, filed Apr. 9, 2001 in Korea, which is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more particularly, to a method for fabricating a capacitor of a semiconductor device by an electroplating process.
2. Background of the Related Art
Presently, tertiary inter-level dielectric (ILD) structures of a high dielectric that can be used in a chip size of 0.10 or less has excellent step coverage and deposition process steps at low temperature. However, the tertiary ILD structure has a problem in that an upper electrode of a refractory metal disposed on a TaON- or BST-based capacitor acts as a catalyst under the ambient of reduction, thereby degrading dielectric characteristics and leakage current characteristics. Furthermore, as a large gap occurs between adjacent storage nodes, degradation of the high dielectric oxide due to H2 may be accelerated.
A related art method for fabricating a high dielectric capacitor of a semiconductor device will now be described with reference to the accompanying drawings.
FIG. 1 is a sectional view showing a related art capacitor structure of a semiconductor device.
In FIG. 1, an oxide film 1 is deposited on an entire surface of a substrate (not shown) to insulate the substrate from a capacitor. A nitride film 2 having excellent etching selectivity with the oxide film 1 is deposited on the oxide film 1. Portions of the nitride film 2 and the oxide film 1 located where the capacitor will be formed are selectively removed so that a contact hole is formed to connect a lower substrate with the capacitor. A polysilicon layer 3 is deposited on the entire surface by chemical vapor deposition (CVD) process and then patterned by etch-back process to remain lower than the depth of the contact hole.
After the substrate is washed, a refractory metal, i.e., a Ti layer is deposited on the entire surface of the substrate and then annealed so that the polysilicon layer 3 is reacted with the Ti layer. As a result, a metal silicide (TiSix) layer 4 is formed on the interface between the polysilicon layer 3 and the Ti layer. The portions of the Ti layer that do not react with the polysilicon layer 3 are selectively removed by a wet etching process. Subsequently, as a diffusion barrier layer, a barrier metal layer 5 such as TiN or a three-component based metal is deposited on the entire surface of the substrate. The barrier metal layer 5 is then planarized by a chemical mechanical polishing (CMP) process to expose a surface of the substrate.
A dummy PSG oxide film is thickly deposited on the entire surface of the substrate. A portion of the dummy PSG oxide film corresponding to where a lower electrode of the capacitor will be formed is selectively removed. Storage nodes 9 of the capacitor are then formed in a portion where the PSG oxide film is removed.
Subsequently, a high dielectric BST film 10 is deposited on the entire surface of the substrate by the CVD process. As an upper electrode, a Ru layer 12 is deposited on the BST film 10 by the CVD process. Next, a H2 diffusion barrier film 13, Al2O3 film is formed. An inter-level dielectric layer 14 such as SiO2 film is finally formed.
The related art method for fabricating a capacitor of a semiconductor device has several problems.
First, as a high dielectric film, the BST film is formed on the lower electrode of the capacitor, and the upper electrode and the inter-level dielectric layer are formed by the CVD process. Accordingly, step differences between cells occurs, thereby deteriorating yield.
Second, since the upper electrode and the Al2O3 film are deposited by the CVD process, the high dielectric film is reduced under the ambient of reduction. For this reason, it is likely that dielectric characteristic of the high dielectric film and leakage current characteristic may be degraded.
In other words, to form the inter-level dielectric layer (SiO2) by the CVD process, SiH4 gas and O2 gas are injected into a chamber as source gases so that SiO2 is deposited by reaction between the two gases. At this time, since a reaction gas (H2) is generated, the chamber is under the ambient of reduction. However, as described above, a gap occurs between cells and the inter-level dielectric layer (SiO2) is formed therebetween. Accordingly, even though Al2O3 film is formed as H2 diffusion barrier film, it is likely that the high dielectric film may degrade dielectric characteristic and leakage current characteristic under the ambient of reduction.
Accordingly, the present invention is directed to a method for fabricating a capacitor of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a capacitor of a semiconductor device in which an upper electrode of the capacitor is formed by an electroplating method so that a gap between adjacent storage nodes is filled, thereby improving step coverage.
Another object of the present invention is to provide a method for fabricating a capacitor of a semiconductor device in which leakage current characteristics of a high dielectric film of the capacitor is not degraded.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for fabricating a capacitor of a semiconductor device includes the steps of forming an insulating film on a surface of a substrate, forming a storage node contact hole in the insulating film, forming a plug within the storage node contact hole, forming a storage node of the capacitor over the plug, forming a high dielectric film on the surface of the substrate including the storage node, forming a seed layer on the high dielectric film, and forming an upper electrode of the capacitor on the seed layer.
In another aspect, the method for fabricating a capacitor of a semiconductor device includes steps of forming an insulating film on a surface of a substrate, forming a storage node contact hole in the insulating film, forming a plug within the storage node contact hole, forming a storage node of the capacitor over the plug, the storage node includes a convex upper surface, forming a high dielectric film on the surface of the substrate including the storage node, forming a seed layer on the high dielectric film, and forming an upper electrode of the capacitor on the seed layer.
In another aspect, the method for fabricating a capacitor of a semiconductor device includes steps of forming an insulating film on a surface of a substrate, forming a storage node contact hole in the insulating film, forming a plug within the storage node contact hole, forming a first seed layer on the surface of the substrate, forming a glue layer on the first seed layer, forming a dummy layer on the glue layer, removing portions of the dummy layer and the glue layer in a first region, forming the storage node in the first region, removing the first seed layer, forming a high dielectric film on the surface of the substrate including the storage node, forming a second seed layer on the high dielectric film, and forming an upper electrode of the capacitor on the second seed layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.